This application relates to computer diagnostics, specifically, testing of computer memory above 4 Gbytes.
Computer data storage capability has expanded greatly in recent years. Testing the integrity of memory subsystems is done by comprehensive computer diagnostics programs, of which memory testing is just a part. These programs verify the integrity and reliability of the bus and memory chips. As memory expands, these programs require fast and reliable access to the ever-increasing addresses within the memory.
Physical memory is the memory that a processor addresses on its bus. In protected mode, a Pentium Pro processor has 236 bytes (64 Gbytes) of physical address space. However, the processor instructions only allow access to the address space from zero to 4 Gbytes. Each byte of memory storage is assigned a unique address from zero to 236xe2x88x921, called a physical address. This address space is flat, or unsegmented.
Segmentation and paging are memory management facilities that allow memory to be managed efficiently. When employing the processor""s memory management facilities, programs do not directly address physical memory. Instead, they access memory using any of three memory models: flat, segmented, or real-address mode. In the flat memory model, memory appears to a program as a single continuous address space called linear address space. Code, data, and the procedure stack are all contained in this address space. The linear address space is byte addressable, with addresses running up to 232xe2x88x921. An address for any byte in the linear address space is called a linear address.
In the segmented memory model, memory is grouped into independent address spaces called segments. In this model, code, data, and stacks are typically contained in separate segments. To address a byte in a segment, a program must issue a logical address, which consists of a 16-bit segment selector and a 32-bit offset. The segment selector identifies the segment to be accessed and the offset identifies a byte in the address space of the segment. The processor maps every logical address into a linear address within the linear address space.
If paging is not used, the processor maps linear addresses into physical addresses. If paging is used, a second level of address translation is used to translate the linear address into a physical address.
Paging, also called virtual memory, allows the processor to map a linear address into a smaller physical address space and disk storage. The processor divides the linear address space into 4 kbyte, 2 Mbyte, or 4 Mbyte size pages that can be mapped into physical memory or disk storage. When a program references a logical address, the processor translates the logical address into a linear address. It then uses the paging mechanism to translate the linear address into a corresponding physical address. The processor uses information from page directories and page tables to map linear addresses into physical address space.
Physical address extension enables an extension of the physical address space in the Pentium processor from 32-bits to 36-bits. The processor provides 4 added address line pins to accommodate the additional address bits. Paging must be enabled to use physical address extension. Both the PG flag in the register CR0 and the PAE flag in register CR4 must be set.
The physical address extension enables the processor to allow two sizes of paging: 4 kbyte and 2 Mbyte. Both page sizes can be addressed within the same set of paging tables, which means a page-directory entry can point to either a 2 Mbyte page or to a page table that in turn points to 4 kbyte pages. To support the 36-bit physical addresses, several changes are made to the paging data structures. The paging table entries are increased to 64 bits to accommodate the 36-bit base physical addresses. Each 4 kbyte page directory and page table can thus have up to 512 entries. A new table, called the page directory pointer table, is added to the linear address translation hierarchy. This table has 4 entries of 46 bits each, and lies above the page directory in the hierarchy. The page directory pointer table takes up 64 bits with some bits being reserved. With the physical address extension mechanism enabled, the processor supports up to 4 page directories. The 20 bit page directory base address in register CR3 points to a 24 bit page-directory-pointer-table base address. This field provides the 24 most significant bits of the physical address of the first byte of the page directory pointer table, which forces the table to be located on a 4 kbyte boundary. Also, the linear address translation is changed to allow mapping 32 bit linear addresses into the larger physical address space.
Presently, most operating systems do not allow access to memory addresses above 32-bits, or 4 Gbytes. There is currently a need in the art for the ability to test memory above 4 Gbytes, as computers grow in speed, power, and size.
If the diagnostics diskette is loaded in the computer at startup, the computer will boot to DOS (or another low level operating system that allows the processor modes to be altered) instead of its normal operating system (usually a version of Windows). Thus, instead of automatically setting the processors to protected mode, they are set to real mode. From real mode, processor control registers can be used to set the processors to protected mode with the paging mechanism and physical address extension enabled, which allows extended paging. Extended paging allows 36-bit addresses to be remapped to any 32-bit address. This allows the processors to set up page tables so that memory above 4 Gbytes can be remapped to any address. By taking advantage of extended paging during diagnostics, all processors can be dispatched to concurrently test all memory, including memory above 32-bit addresses. This memory is tested in blocks by mapping, for example, a 1 Gbyte block of memory with 36-bit addresses (i.e., memory above 4 Gbytes) into 32-bit addresses. This remapping is done by setting the page tables through which the processors address memory. By directing the page tables to higher blocks of memory (blocks above 4 Gbytes), the processors can address this memory with the existing 32-bit addresses.
In the preferred embodiment, the processor is booted from a DOS 6.2 diskette, and diagnostics are executed. The program places the processor in protected, paging, and physical address extension modes. All memory above 3 Gbytes is tested in 1 Gbyte blocks, until the end of memory. Note that the selection to remap memory above 3 G,bytes is arbitrary, as is the selection of testing in 1 Gbyte blocks. All memory could be remapped, only memory above 1 Gbyte could be remapped, etc. The 3 Gbyte threshold is selected for convenience, and because of the xe2x80x9cmemory gapxe2x80x9d present in some systems, which causes some memory below 4 Gbytes to be unusable. Alternatively, a 64-bit start and end address may be specified to test a specific range of memory if desired.
In the presently preferred embodiment, the system processors are directed to the same 1 Gbyte block of memory. They divide this memory among them, run the testing algorithms, and switch sections of memory, continuing testing until the entire block of memory has been tested by all processors. Then the processors are allocated a new block of memory for testing, and the process repeats. When the entire memory test is complete, the program sets the processors back to real mode and returns to DOS control.
Note that, in the preferred embodiment, the diagnostics diskette boots into DOS version 6.2. This permits the processor modes to be properly set, as discussed above. However, a more general consideration is that DOS is a lower level, cruder, and more robust operating system that any of the Microsoft Windows ((trademark)) operating systems. The Windows operating system is a xe2x80x9cseamless web,xe2x80x9d which takes control of many system settings, including some memory mapping and page table functions.